Tools & Technologies
VerveTronics is a renowned and proven FPGA design centre with advanced capabilities in Xilinx, Altera, and Actel devices. We have design expertise on all major platform technologies and advanced tools such as Synplify Pro, ModelSim, MATLAB/Simulink, System Generator, ChipScopePro, DSP Builder and SOPC Builder. Besides advanced capabilities referenced below, VerveTronics is quite capable of providing cost effective solutions for simple interfaces or logic designs on low cost, low density PLD devices. VerveTronics can take up design from concept through specification to FPGA implementation and further can make it migrate to Structured ASIC.
- Design: System Verilog, Verilog and VHDL
- Simulation: ModelSIM and Verilog XL
- Verification : System Verilog and SystemC, C++
- Synthesis : Leonardo spectrum, Synplicity, Precision RTL and Xilinx & Altera
- Implementation : Xilinx & Altera
- Timing : ModelSIM, Synopsis and Verilog XL
- Physical design: Cadence
- IP: RTC, UART, I2C, RS-232, USB, Flash Memory, LCD Display, Touch screen Panel and Audio/Video Interfaces
- Bus Interfaces: PCI, VME, AXI, APB, and ISA
- Network devices: Ethernet, Gigabit Ethernet, IEEE-1394 and TI/E1
- FPGA: Xilixn Spartan, Vertex, Kintex& Altera Startix, Cyclone
Good quality HDL code ensures good quality of results from synthesis and facilitates efficient reuse. VerveTronics has extensive experience in creating a broad range of designs using both Verilog and VHDL, based upon a robust set of coding guidelines.
We have extensive expertise in low-power design techniques and are skilled in IP integration and design for reuse methodology. Our highly productive design team has proven ability in taking designs from specification through to fully verified RTL.
The ability to develop a high quality verification strategy is one of the key activities that will determine the success of your ASIC project. Get it wrong and you are looking at a silicon re-spin with typically a 6 – 12 months delay in getting your product to market with substantial cost and revenue implications.
VerveTronics can help identify the right verification strategy for your design, one that will provide high confidence that the functional requirements defined in the specification are indeed implemented correctly.
Some of the methodologies and techniques we employ are:
Verification planning and test bench development Advanced techniques:
- UVM, OVM, System-Verilog
- Assertion-based verification using SVA
- Coverage driven verification
- Behavioural Modelling: MATLAB, System-C / C++
- FPGA prototyping – emulations and system demonstrators
- Low-power verification techniques – power estimation, CPF/UPF
- Register abstraction based flow enabling design and verification reuse
- Design of always-on agents and protocol checkers
- Cycle accurate C modelling of module and complete systems
- Use of PLI for co-simulation of embedded processors
Device Fitting and Timing Closure
There was a time that just setting a global maximum clock frequency would constrain an FPGA design. Modern FPGA devices support multi-clock domains, multiple PLLs and high-speed interfaces such as DDR3. FPGA tools have matured offer the past few years, and now include accurate static timing engines supporting ASIC compatible constraint scripting languages.
For reliable operations across all process, temperature and voltage corners, timing constraints need to be developed and static timing carried out after each fitting to ensure that the design will work in the intended environment. VerveTronics apply their expertise developed on high-complexity ASIC designs to generate real world timing constraints and achieve the required timing in the optimum speed grade device.
VerveTronics has all the expertise needed to support the logical implementation of your design (Synthesis, DFT / ATPG, STA, Formal verification) and interface with your chosen layout team – this could be VerveTronics, in-house team, 3rd party layout company or an ASIC vendor.
Development of synthesis scripts to target the design onto a specific ASIC technology.
DFT / ATPG:
VerveTronics have expertise in developing a complete test strategy for your ASIC design to deliver high fault coverage. This includes :
- Scan / ATPG
- Testing of embedded IP (e.g. hard IP / Analogue)
STA / Timing Closure:
VerveTronics can develop complete timing constraints to support timing driven place & route tools and full Static Timing Analysis on the post-layout netlist, to confirm that the design meets the required performance targets prior to tape out. We are skilled at working closely with the layout team to achieve efficient timing closure on technologies down to 65nm.
VerveTronics undertake formal verification to confirm logical equivalence between RTL and the synthesised netlist and then gate-gate checking on any subsequent versions of the design as it goes through the design flow (DFT, physical optimisation etc.)
VerveTronics can support the physical implementation (Floor planning, Clock Tree Synthesis, Place & route, Timing Closure and Physical verification) of your design all the way through to generation of GDSII.
With detailed knowledge about the design gained through the design and verification activities, VerveTronics are perfectly placed to undertake the physical implementation and ensure that your design reaches tape out as quickly as possible.