Logical Implementation

“VeveTronics has all the expertise needed to support the logical implementation of your design (Synthesis, DFT / ATPG, STA, Formal verification) and interface with your chosen layout team – this could be VeveTronics, in-house team, 3rd party layout company or an ASIC vendor

Development of synthesis scripts to target the design onto a specific ASIC technology.

VeveTronics have expertise in developing a complete test strategy for your ASIC design to deliver high fault coverage. This includes

  • Scan / ATPG
  • Testing of embedded IP (e.g hard IP / Analogue)
  • JTAG

STA / Timing Closure
VeveTronics can develop complete timing constraints to support timing driven place & route tools and full Static Timing Analysis on the post-layout netlist, to confirm that the design meets the required performance targets prior to tapeout. We are skilled at working closely with the layout team to achieve efficient timing closure on technologies down to 65nm.

Formal verification
VeveTronics undertake formal verificationto confirm logical equivalence between RTL and the synthesised netlist and then gate-gate checking on any subsequent versions of the design as it goes through the design flow ( DFT, physical optimisation etc)

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