Functional Verification

The ability to develop a high quality verification strategy is one of the key activities that will determine the success of your ASIC project. Get it wrong and you are looking at a silicon re-spin with typically a 6 – 12months delay in getting your product to market with substantial cost and revenue implications.

VerveTronics can help identify the right verification strategy for your design, one that will provide high confidence that the functional requirements defined in the specification are indeed implemented correctly.

Some of the methodologies and techniques we employ are:

  • Verification planning and testbench development
  • Advanced techniques:
    1. UVM, OVM, System-Verilog
    2. eRM, e
    3. Assertion-based verification using SVA
    4. Coverage driven verification
  • Regression management etc
  • Behavioural modelling : MATLAB, System-C / C++
  • FPGA prototyping – emulations and system demonstrators
  • Low-power verification techniques – power estimation, CPF/UPF
  • Register abstraction based flow enabling design and verification reuse
  • Design of always-on agents and protocol checkers
  • Cycle accurate C modelling of module and complete systems
  • Use of PLI for co-simulation of embedded processors
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